The present invention relates to comparator circuits.
Known comparator circuits are arranged to compare a first and a second voltage and to provide a first output if the first voltage is greater than the second voltage and a second output if the second voltage is greater than the first voltage. Typically, these known circuits require a clock signal having first and second levels. The comparison carried out by the comparator takes place when there is a transition in the clock signal from the first level to the second level. The known comparator circuit requires two clock edges to complete a comparing operation. This is undesirable in certain circumstances.
As the comparator requires two clock edges to complete a comparison, the comparator circuit will be on for the entire clock cycle In particular, current will not only be drawn in the comparison phase of the operation, but current will also be required during the evaluation phase. This is undesirable if the power requirements of the comparator circuit have to be minimised.
It is therefore an aim of preferred embodiments of the present invention to avoid or at least reduce at least one of the problems of the known arrangement
According to one aspect of the present invention, there is provided a comparator circuit comprising: comparing means for comparing first and second voltages; current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.
In this way, the drawing of unnecessary current is avoided. As the comparing means are switched off when the comparison has been completed and not when the clock signal makes a further transition, it is possible in embodiments of the invention to make use only of a single edge of a clock signal to control the entire comparing operation including the evaluation of the results of the comparison.
Preferably, means are provided for preventing the consumption of current when said clock signal is in the first state. Thus when the comparing means are turned off, it is preferred that the circuit not draw any current.
Latch means may be provided for latching the result of the comparison carried out by the comparing means. Thus when the comparing means are turned off the results of the comparison are not lost.
Preferably, said comparing means is arranged to complete the comparison prior to the clock signal changing from the second state to the first state.
Said current circuitry may comprise logic circuitry receiving said clock signal and an output of said determining and switching means. The current source circuitry may, in use, be switched on when the clock signal makes a transition from the first state to the second state and switched off when said comparison has beer completed by the comparison means. The current source may comprise a transistor.
Preferably, clamping means are provided to ensure that least one node of the comparing means is connected to a power supply and said at least one node is at or near the voltage of the power supply when the clock is in the second state. The power supply may be ground. Thus before a comparison takes place, it can be ensured that the at least one node is at a known voltage.
The determining and switching means may comprise keeper means which are arranged when the comparison has been completed to hold one node of said comparing means at or near a value of a voltage supply. The voltage supply may be a positive voltage supply.
Preferably, a second node of said comparing means is maintained by said keeper means at a different voltage supply, when said comparison has been completed. The different voltage supply may be ground.
Preferably, the comparing means comprises a pair of transistors arranged to receive at their control terminals said first and second voltages.
The determining and switching means may comprise a pair of transistors arranged to remove the current path through the pair of transistors of the comparing means when said comparison has been completed.
The comparing means may comprise a pair of cross coupled transistors and a node coupled to each of the transistors of said pair, whereby in dependence on the relative sizes of the first and second voltages, one of said nodes will have a relatively low voltage and the other of the nodes will have a relatively high voltage, when said comparison has been completed. The nodes may be the same as the at least one node.
Preferably, said determining and switching means is arranged to receive first and second inputs, whereby when said inputs are different, said comparison has been completed. The determining and switching means may comprise a gate, such as a NAND gate.
The comparator circuit may be a differential comparator circuit. Alternatively, one of said first and second voltages is a reference voltage.
According to a second aspect of the present invention, there is provided a voltage measuring circuit comprising: means for comparing a first voltage indicative of the voltage to be measured with a second voltage; counting means; means for temporarily reducing the first voltage applied to the comparing means so that the comparing means provides a first output which differs from the second output when the first voltage been applied to the comparing means without being reduced, wherein the count provided by said counter is dependent on the size of the voltage to be measured.
Preferably, the reducing means comprise a first capacitor which is charged when the output of the comparing means has said first output. When said comparing provides said second output, said capacitor may be arranged to be discharged. Preferably, the amount by which said first capacitor is discharged and/or charged is dependent on the size of the voltage to be measured.
The reducing means may comprise a second capacitor which is arranged to cause said first capacitor to be discharged into said second capacitor when the output of said comparing means provides said second output. Preferably, said first capacitor is bigger than said second capacitor.
The reducing means may comprise a resistor connected between the voltage to be measured and the first voltage.
Preferably, the counting means is arranged to count for a predetermined number of cycles and the count at the end of the cycles is proportional to the size of the voltage to be measured. Preferably, said cycles are clock cycles. Preferably, the voltage to be measured has a maximum value and when said voltage to be measured is at said maximum value the count is equal to the number of cycles. The count maybe linearly proportional to the voltage to be measured. Alternatively, there may be a non linear relationship between the count and the size of the voltage to be measured.
The second voltage may be a reference voltage such as ground or any other suitable reference.
The inventions described in the first and second aspects may, but not necessarily be used together.